-%%-////---/-.+/--+------/------/--0+--/-/-----.-----ÿÀ  ¥2" ÿÄ     ÿÄ J    ! 1AQ"aq2‘#BR‚¡ÁÑ3br’¢±Âð$CSƒ²á4c“%DsÓñÿÄ   ÿÄ *  !1AQa‘"2q3±ð#b¡ÿÚ   ? ¼QxJQaÍuò¸Zö Úü8,ÐÚú "SSn<rçù–´âE—^ªBÖ9À\†¸ÔÁT­ÃÛ5 ëd´³Í#Ý;Þ38œî ¶H£M:wÎ3…³…âpÔF&‚FK¸9„â4àGEõªfÿ ‘ñ(ßw­pŽF|È¥ù®häðÍѶ¹‘[ÒinÙW¶ùñY˜Q{›K"išÒ[Ú8žë\F¹@-?v"ÔU”,ìöžkÿ {I‡£šÍ?e ríV .............................................................................................................................................................................. ............................................................................. ÿØÿà JFIF    ÿÛ „  ( %!1!%)+//.383,7(-.+  -%%-////---/-.+/--+------/------/--0+--/-/-----.-----ÿÀ  ¥2" ÿÄ     ÿÄ J    ! 1AQ"aq2‘#BR‚¡ÁÑ3br’¢±Âð$CSƒ²á4c“%DsÓñÿÄ   ÿÄ *  !1AQa‘"2q3±ð#b¡ÿÚ   ? ¼QxJQaÍuò¸Zö Úü8,ÐÚú "SSn<rçù–´âE—^ªBÖ9À\†¸ÔÁT­ÃÛ5 ëd´³Í#Ý;Þ38œî ¶H£M:wÎ3…³…âpÔF&‚FK¸9„â4àGEõªfÿ ‘ñ(ßw­pŽF|È¥ù®häðÍѶ¹‘[ÒinÙW¶ùñY˜Q{›K"išÒ[Ú8žë\F¹@-?v"ÔU”,ìöžkÿ {I‡£šÍ?e ríV .............................................................................................................................................................................. ............................................................................. T_V5 V?VSVgViV WX$XXXXXY*Y?:]Cz]7]>]?5^6u^$^0^3_R6_[_L_2aAaGa]a8xaNaCb[Db;bWbM4cBc"cCc3,d1`d@dYd?-eHmeCe5e0fftYggvhi3iQi4eisij3$jXj"sjj j jj$j)k?-k\mkIk:lOl[lKrIsA\s;sOs'*tFRt=tDtCuA`u"u[u!v}v>pw>w,wKx>gxHx;x"+yANy@yDyjz9z3z@zL0{K}{{ `|Hj|E|E|P?}F}.}?]FA @?ـEk_Dˁ::K4p3,4`>9ԃ4qC^<6)E`9235G }62Շ/B85{<+@4[AP҉i#BЊZG.-M\TBڍ0;N=>Ȏ??GA1ɏAE=GDːiDzO|HLՒ,"OBՓ?"X<{NB8J""HɕO bel1Ҙ$ %.!T&v%6Ù%% %F%l%##ܚ&*7b"21'd Ü40@Skt|'&(ӝ'0$)U")-̞17,$d+.   * .9V!f *ʠ(&88_ҡ"-.C-r3#Ԣ%&&E1l8 #+%Kq3`̤`-& ֥ 15I1358NTX784*m0!ɨD 0 =!Jl1{+٩B=CD  0=-[ %ݫ%=NBVĬE\(1"$<kaͯ74$,Y'.ΰ@m>/%;&C';ec-ɵ$W/Mm1&BX2>νG MUWF4Bw2+ǿ:9:(9cgW&M?9d',MTJIF77~@0M(pvd9L)7eN/:?4""7)Z$"#6"S3v2 0*3[42"$2?3r36JR:,-.31b1070/#` .324;3p(/%#U1y22$6&O'v'59*W6##$9!^"'- :S!j.+;":]|!,861O4*+ ?59u**3)9c{.*/Z+x$,#67T106&@.T13#784p,($# -D)rE&"499n631Ld4v3'$:A&|A63;/o7()*1D,v1FEbs'G8#R!v&%3GY!D#,L'i,>)!''I8q'%+$B_ %@&] "8);$e")#'M>-|3=Rq(55#Y7' _(i%4'%5;*qO40!2R%3%+IU_#cD8%.+4Z1iC+o$ED&<c Z7<Et 6(.;W"!"**.U%!61'5C]0 !! 'C k    6  # 8 X v  A  " % #D 5h  ( )  ! 5 G \ o  !   0 4 P :p  > '(@+W-#)44F${+ 3;!3];/!47l-)=!"D1b:3:"=]-3#&!HZo&, ?"`   265l%-$#*1H2z05+3C2w!-$!> `E-FM<.-1=2W&'/? 0IWz!-%",H%uT %$%J<pC#9 9O < !  !&&!M!'i!4!!'!$",""I"l"""(""" #=##Ca##'###$ ($I$#Q$1u$$5$3$*1%"\% % % % % %"%%% &7=&u&&&&&&'+'%A'g'(')'/'(' (0H(*y( ((6()*)G)#Z)+~))2).)$*:*K*#\*,*#*%*** "+%0+!V+%x+?+(+#,)+,3U,+,<,4,%'-+M-:y-:-?-+/.3[.,.%.-.(/<9/v/1/ /3/%0=0<Z0003001814T11$1112+$2)P2,z2@2.23".3+Q3$}3)333$6a6F<7R7.7/8$58'Z8*8.8*89?&9)f99979+97(:.`:::::#: ;%;@8;Oy;/;3;/-<6]<1<4<=<O9=J=>=*>+>>6j>,>)>*>2#?&V?+}?1?.?< @ G@0h@@2@(@/A1CA0uA0A'A0A'0B.XB0B#B+B2C;CVCuCCC5C7D?D"\DD1D;D E$E0=E3nE4E2E] F,hFF-F1F2F//G._G+G+G-G#HO8HqH)H4$IYIRwI(IBI.6JAeJ5J,J. Ks9KkKL6LOLlL"L+L!L&L+M2IM%|M/M1MINNN(nN7N,N0N$-OFRO)O'O(O(P"=P`P{PPPPP P#QBQ#ZQ$~Q"Q&Q%QR 0RQRpR&R&RR&R!S=SUS(lS#S#S#ST!T ATbT$T$TTT(U&/U"VUyU/U+U+U2 V2SV7V7V/V=&WdWW*WWW"WX:X&NX(uXX XX/X/,Y\Y vY0YYY(YZ1ZCZRZ1jZ ZZZZ[[.[J[=h[[["[!\!(\!J\!l\+\(\8\"]!?]a]]]$]]*]+^8:^s^^^%^*^1_-L_'z_3_(_@_@`U`;n``&`2`6a-Lazaaa*a7a8+b9db9b2b' c'3c[c qc8c&c-c3 d2AdHtde"e(e%fg$-g4Rg%gg"6h0Yhh hhh i)iHi.hii(xl!ll.l m9m Sm_mzm mmmm$mm"n2nAnZnln+n/n"n* o6o7Vooo ooop2 pSp2sp<ppp q7/q6gq-q5q6r$9r^r`vv;vAvbw&~w5www/w%/xUxgxxx$xx'x!y4:yoyy!yyy yy#z)8zbzqzzz!z3z#{={Q{k{{{#{{,{B|&I|2p| |1|2|1)}:[}#}+}&}' ~%5~'[~%~9~$~='AeBB-&=$d.-)'0&X%Ł(ց#"#F1d)*ڂ5$;<`0)΃(*!.L.{,ׄ\NS,+χ D<b.%1W,w1-։-/2Rb!Qs92͋4 5CY"q$?ҌA+T0,,ލ* 6$R(w*ˎ217L6<' >-Z.ʐ Аڐ!$֑$" C-ZJb!v7;A"^#!?ǔ89@zD,ݕ0 5; q2Ŗ2ؖ" 7.%f ƗH/)-2W7)-Wt;:ޛ9-S$6Eݜ2#,V4C4C1Au,+a%r'5$--Iw3)ɠ60*[u-ҡ.50P!+Ϣߢ- .:=iD!)/8h~*/3$'X((ƥ%%';:c;<ڦs{e7m4Ũ%8 4Y7*Ʃ)))E]o-ͪ.,*W%,$1Q7->+(1T(5409j!ٮ'-C]4|$ί4(3>3rT/<+4h'+ű5%'$M0r"Ʋ0"&41[63ij,%%Kc! δ3H]*n!1ӵ!!8/Z(!( 3Mh %#)Ak ø3ݸ ,3M&&8Ϲ$-G"d)&˺)(#Rv-ƻ0#%4I~e&!SHJ52:2m17Ҿ= @H@ʿfI0h&;+E!Xz>Z+-98-2f11/.-\<z%&&#J&h$!;iVk;,h 337.+(Z;()@-j$6E):,d**741!f(/ +=3i3!""0S q$!>$Ot,%&!'H'p&:%*9+d  <<$;Zz)68$W-|(%KIE3'/+5#a#:*%,Rf{/)Ee &"0N3i !A@<&@%Mf@-/BDr3O-e,)! ','T`|,* (54^0. #30W**&1@/r*C#5Lav,6 8C6|24,Cb )#! :[q!) %4J.c2',%*R$} 4F ^5)=<Zq"&4" (,Ut%$6Lcy6*"0S r~%)(<Yo#$'*Gr BA!/Qm~ &3)9]6"#!7%P+v&$ (G*a.&$>& e,&',!8N&' )(Rp'(+3<[nD1M$h-)>]o&*11C_2}*+1"Q3t#&')!Eg)y-077:7r'*47O %9#( L-mD())F1p@260!g301 ?![9}:/#"/F#v1*4.L5{/0*=M#j&   /Pp!&75;0q ^5*U4)))  3Ts-3.L{(8)4  ^ /l /  ' ! - #L &p " ) # ( 1 G ,V , $ @ C 2Z  6  -  *8 %c  1 - + 2!*T/C,,@m?E4.:c=.' 63j-#"87O::C#]"$("+5&a  %$$Jo-&6"Or,4(/ O$p2%-?Pi'+.)$E j#2!1H^t# 0=F'%  ";R:g$'A7`1$*, G7h?$:*@k4*& = *O z :    =!:F! !! ! !(!0!1"#E""i"+""&"<"#7##[#+##)#(#)$H$f$1y$.$ $$%$%5%Q%(k%(%%%"%+& ;&\&1x&&& & && '1&'X'%g''''''%($7($\( ($(*((- )":)/])+))+)@)<*$B*g*!z**$*'*+4 +>+0^+4++$+,$,%D,"j,!,,+,*,"$-5G- }-&-(-3-.#.9.P. k...%..7 /3C/ w////(/"0#+0&O0)v00'00T02M11111@1A+2)m22$222 3(03Y3w3"33353G$4*l434&434;&5b5*y5+5$5.5'$6#L6&p666/66,7'B7!j7"7(7'788%.8T8o88898)89)9!C9e9 }99#9999:12:(d:/:::#:#;>;,\;;;;";)</<!F<.h< <<(<(<&=A=5a===4=4><>'T>&|>&>>2>;?<Y?/??#?2@&;@)b@!@@ @@2A15A)gA+A&AA4B%5B%[B"B6B@B%C#BC0fC8C2C.D12D2dD1D1D6D92ElE&E%E'E0F&2F&YF-F0F+F* G*6G*aG!G)G1G1 H0R9+S-eSS+S%ST% T3FT2zTT!TT U-U MU(nU%U!UUU$V@VYV rV"VVVVWW1WFWcWsWWWWWW)X+@XJlX#X8XY))YSYjY)Y&Y Y"YZ6ZHZdZ9ZZ"Z7Z7&[.^[>[F[J\@^\2\,\\9]"W]z]!]]]6]"^%5^)[^)^^!^^f_h______ _;`/Y```&```a#5a1Yaa&aa1a#b=b1Ybbbbb bbc+cIc,cccXcZcSd1md'dd+dee%(e7NeeeAee f$f;fZf<qf"f.f.g./g.^g.g0g/g-h/Kh){h(h(h&h(iGi.Xi@i"iij#j,Bj3ojjjjj# k0k%Pkvkk*k"kk-k-lCl&Yl2l.lllm3mOmkmmmm"mmn%n'Cnkn"n)n)n)n)o:oPopoo o5ooo3pBpYpwpppppp q #q Dq!eq#qqqq r'r=rYrvr%r%rrr*s>s^s{ssss!st4t$St"xtttt9t=)uguu#uuu.uv+v$Av#fv vvv*v)v+w*Bwmw8w9w*w9x;Wx;x<x. y/;y&kyJy6y0z$EzjzXzz*zE"{:h{{@{/{)|I|H\|B|7|" }'C}k}"}}V}V ~5w~L~0~#+ Op!79?"y?)-;$i*ȁ߁   ! - 7D$d#+ ق   ' 1 ;2Gz  ΃5'F+n DŽ܄ "?6V Dž܅ ++I%u.ʆ 7 O)\ ߇/:0"k,Ԉ4"2Ug |ω   , M%i-!؊"5Sr+ ؋/-)$W|@ό$.A Q_0|֍GO o($'4.!c( Ə( 1'OUwD͐-*@"k)#Ց .(Ox/8 )(Dm.*,ߓ "*0M~.˔! ($Mk.ϕ!*'@R *#ߖ2+6b#՗ >$^  3Ř6#0,T-62(K+t:9ۚ-0C't))ۛ./4%d9JĜ=AM>;Ν *2]y).(F!d"618!K"m!ʠ# %;T%o1ա2:R2g1(̢* :Tp70)1*&\**6&],o05ͥ" =&^   ȦDѦ!5!W$y/ Χܧ6 0"< _'l($&% /-O.} %ک @ _:2%"75S3۫4!,N%n4)ɬ)&"D4gԭ'"0>oAۮ 0!1R' (#L%lȰ!ڰ$5%Z#(>ͱ) $6E[-.ϲ5!4V&s:)ճ@^x&%ٴ5Rm )ƵD.s!̶5Sn-'ѷ,(&8O029Qe#:8޹)AYt5- ,8+e$/ͻ1/0B0sü,IB,Dν1Lc'|53ھ!,0(]@>ǿ"')'Q)yF@/+1[1(F#/%S&y "0&"&2I+|%#5!(+J v',$CQ%< I3cF 0/-`5%:#CgDn0(: -H%v+'' (3&\0.G'? g0*5+,%X6~$ 5.N}%,+ #6#Z-~'+;,Z*%0 *=>1|'340 e%r%,)'H(p#*7* "K(n',-N+i(D1'N>v497$'\2('r'{8+b"k#+@56U4%7)?-i>581/j-*00$6U2; &3Cw*$3"3V'"#+,H#u, *3^p1)B`%u%*0%2,X1:!<<Q.!=2p*7! -@"[%~ +!%*.P  !"7Tn!#)++'5S4%/+,:#g %!1Ne#''0DLi" =N`&{$ &$Af!'09 j #%'>OFh!5G["oA)Y$$!'2J!a% %B a -6-*d*/ !B:X 2"Lo!!@\w1+!3O"k"%."Fi%.!E*g"$)?Zv'!%5Ja,(: M[jy .@Rdu&5FUfw '-5)c,+00)Z2s1&3P1W$)" 2S!r,"",34,h('1+D d !3/9c&.<1P0+A%!'G:o!(" )1 4[ -   # F DU # +    < E [ q 4s $4MCSC;JIb7"9>A[h]E?N(HwnB/YrNI'eC51B9W|AOUf<m2on   !?1!nq!!4!+"#F"j" " ""$"*"D#dG#H#9#/$a$N/%?~%5%S%LH&M&4&E'C^''ED((H)L)I;+M+B+>,TU,',U,@(-Bi-H-C-'9.ja../=90Kw0/0L0?@1I1<1'2=/2Em2L2l3;m363F3R'4Xz44 x5O5O5O"6br6W6.-7D\8c8C9%I9o9I:FN:F:o:HL;=;=;7<oI<><5<6.=Ae=9=p=R>?@?7?W@<m@7@6@7A QABrA7A0ACB7bB>B/B@ C7JCICSCo D@DDgEKF.OFZ~FF[G@H4OH@H1H2H3*I3^I5I2I5IT1JUJIJe&KEKOK|"LSLWL/KM{MCNGKN'NENKOJMOCO'O'PL,PoyPP~Q1{SS(S%S!T&#T%JT:pT%T%T%T%U%CU#iU#UU&U*UV$V4V-W$KWpW&WW:WX$XBX^XgXoX(wX'X)X(X3Y*OY#zY*Y1Y3Y:/Z#jZ2Z8Z"Z[$[ +[ 6[C[G[V[v[(["[[[,\'-\)U\&\7\ \&\&],D]5q]>]4]:^'V^-~^.^.^5 _@_CV__ _%__$_`63`j`o`p`+daaa'a<aA,b;nb7b8b@cV\chcCdD`d6d6d*eE>eee5ee9e6(f _ffHfKf&gJCgg(g(gg% h@0hqh#h"h8h i&iBiQiHYiiii;kk&k9l@l+_lyl m>&m<em,m&m*m6!nDXneno/p&5pA\p$p p'rqr/hs&sswsJvWvFw1{J:{-{>{U{MH|W|Q|5@}v}6},}}KI4K~IʁoWN)MІGdf*ˇMJDOQ߈61Ch1Xމ7dGK*:e_49T2&&*'Q4y$ΐ%'93a%3;+?W,w34ؒ: H$e23"3?5sO=,7-d--,-4I,~!$͖78*5c<8֗/M(j.#˜-12F!y$$ؙ'%>B0=')'Qy!#כ$ $1Vp7 ߜ3'([8% )4D;y125/P0A֟?@X@1ڠ, 9W!u!͡5&E/e$0Ԣ$%*6P044"87M98$57J931-"#P6t2ަR3Ey6;Ƨ88;tȨ9٨66J9:>37r8Ū1702h&«A;#0_QK. A1b%J="C(f&!خ(%/DMt(¯C+/([%14ܰB.T'(8Ա( (6._ "ϲ'>Qg})ӳ&($Mj;,ô'(A0`0#µK*2]wc/۶U )a44 5+.*=Y.-ƹ>*3M^B-1-O}<&һ+%W@#f>,)2 6S2jS(|)JM&]# b.iW A'-i@%)5*_386.MF4+L)Bl}!!&%"$Hm>&$(Ml;**(<=e.2+1]t+#'"?C_! 5@4,u15$Di8 8.8N!:A:&Ba'(5(D6m2F+'J;r@&K@bC2>*Y)&.'7_}5'*?$_&'8; H+d3++94V2+,-=G<%4$D%iI0M&Et0/0:L5+,2@I3d#6C"z8,X$p,,6D&#k>?BQ$p'!):)d)y&"%(Cl=G B+O {#1#9*TB;,*+Vk'&#,AP%3Sq,".. 6:q1.$'?6V3',30G1x91!#S;w=&'*%RCx3,8;V6H;,N6{FFL@6A0+7%c @?,E9r,-L"Tw; @^-| "2-A&o49&$/K1{3$ k/QT5B>x,/63K.'I* K)gG3> 6L$*5GL_04%1Z835G/ewXC6-z.?63N07,5 9N 6 P " 53  i ; 0 ; <3 ;p ; / ; /T : : $ - 8M    & '6)1`!=C!(e/7<9R[(7/P=99-2.`4U{7-9!D='>+G@],/p##=a"~+"((/B"r=2EL%j4-9)-IW2!"&&@g#!2T#o&*.&;)V$%3'!Fh0+ #1U$r''%  E +f #   / * !*K!1v!1!6!6"/H"Hx""")"#(9# b###!#1#$$">$5a$5$$#$8%G%^%3w%%%%%6&&8&_&w&&&&&&G'!]''''''(,;(*h(<(#(&():)M)+f))3)7)A*W* o*"*%***1+.6+3e+A+1+< ,J,i,7,,,,),<!-0^- -$--0-A.Ba.E.>.7)/(a/'///H/)$06N04060p0b2&2*223#3?4$W4|4"4>!5$`5%5$5#5$5#6$=64b68619: !:5B:x:4:::::;;7;$H;m;%; ;;;;9;73< k</<<6<=2=#C=g=v=&=<=!=4 >CA>>>>E>7?-L?3z?3?&?+ @5D'TDF|DDD_EhE;EEE<E./F^FsFFF.FF1G#CG8gGGG)GGH4HCH&`H-HHHHI'#I>KI&III IJJ$2J WJ2eJDJ/J> K*LK=wK>K=K82LkL*L(L)L'M(0M'YMDM(MMBNFINFNFNO7-O+eO3O6O&O3#P&WP%~P'P&PP( Q/4Q.dQ#Q;QQ0R0DR>uR*RER0%S1VS-S)S-S-T+[<*\g\~\\\&\\I]OK]6]>]2^.D^0s^^^2^/_ E_f_7{__;_< `CG`%`%` `1`3*a^aaaqa waa-Wbbb$bb1c&4c [c|c d(d#@d$dd=dd@d!#e'Ee'me#eFe4f85fnfGf1f7g2@g)sg?gg>g+7h<ch(hh$h iK!k2mk,k5k!l%l35lil l,lllmO)mPym>m. n)8nAbnOn:n4/o?doMo?oN2pOp4p#qi*q*q'q>q+&r/Rr6r"r4r'sF9s4s"ss1st/t1Htztt4t"t3u;uPu_u4|u2uEuJ*v"uv-v6vv#w"7w0Zww4w4w* x7x*Qx+|xxx*x4y?Hy@yyQzmz8O{"{;{({;|7L|=|*|)|)})A}bk}8}7~1?~q~&9.`4?1@61w3*݀7<@'}3ف!$9^/tÂ݂*:%#`3:(43QY/߄8=H(5C%)$O7t&ӆ0'$&L2s51܇*(9b!y Ј! (AWn.#ĉ26S(m1"Ȋ#"!)Dn"ŋ݋ 0I+eˌ݌6+D1c%$;!>V#p',Ԏ!!#7E"}%!Ə(30-dC&֐&b$5[X!r>4Ӓ47=9uI>>8w&7@)xH 0 =(N$whS56>)=h54ܙ46F5}#Aך%0?0p0$қ0$(0M#~""Ŝ" *LL .282W6:*V,/(ޠDLL44Ρ**D?o<$'19,k,Cţ9 ECE)Ϥ)#A`,|")̥*(!QJ%$¦"< 'G&o-6ħ-*)TGr(3)AP>_>ݩ)&#)J(t4AҪ))>-h96Ы\'G0̬%(#L5j' ?+H'tŮۮ9T,o&ï *& ?`6ְ -Mm> A 1L%~GQ7>v?6ѳGP!e%!Iϴ6.,eе&-vB/0%>@C8÷!(+G5s7(+*-V6>*V%,|ƺ-Me6}>@>4:s<%%Dj+})'ӽ#$#Dh-Ҿ2$)Cm-+$"4-W:7/(Fc*!)>C3IHI#h++7'3D#x#2'DlD 5R .( 3'E/m+-M"k!,!-#M.q JI$)n!/,N@{G8=\%|,--C$c+#+ 7)Q${< 1,0,]$0B#?)\*!5* 4*O*z/F"?WqJ#8X1v4 0@#q%.2>3$r'!=6P2l1%+@#.d3*0)#M1h3=B BOB,585X=#,A'_"3M(J0s%16H3|:;+9<1v$; (&@OA9+ 78)p9*-<-7j?5;6T"'&!'I&i'$$0-^8z5'" uC"*20:0k0#%":1X70'"J3f91 8*:c)&# -)L(v+%/! 50B0s)?M;\2-"2=3p A;1.7`17F#I9m0 NIH288/T&:8*V)DCE4DzJ''Oa,s&:!)$(Nw$*5`y2% /#Im/6"#C#_/+  '>['k'3/*0J4{3"7Nl,'%(."WzH/ 1$V hC.9h# !&=$7b'-/# ADL)C1As#E.$So0E2FJ^N  /0=?nB('/Br.H**30^%*22#Fj92 9Eb1{1 ') Q m + #     # /D t ; 0 # $ .@ /o ; 5 3 7E =} ;  + +< ?h 3  2 N%t%z#/A4I~D> 1@!r*)$)%:`9 &3A9{+)+!Km>8$)<W'h%-#+@lQ~8! +-KJyK.!?-a%%.!%$G*l<=X6k?0>MR.6(&<O-.)B5V3(""'-J'x'(HA[5& 3#M*q-$ 5) '_ 3   ( (%!&N!-u!!!!!!1"K"+h"6"'""2#28#*k#(#J#$ $%/$CU$C$$'$$#%&H%o%9%=%;&8@&"y&&&3&'&3'"S'v'$''='<((N(7w(%((7('')'O)#w)=)L)%&*"L*4o*=*6*2+5L+6+5+5+7%,:],,*,(,1 -2>-,q-,-8-2.)7.,a.,.,.#., /79/0q/3/4/( 06400k0?0!0#0%"1'H1p1=1)1!1D26[2%2%2!23E3-b3>323)4B,4Io41464@"5)c5.5.5J5D661{68626K7!e7&76777?8!]8,8,828/ 9/<9-l919494:C6:0z:?:G:@3;,t;$;);$;<!3<0U<7< <%<#=$)=#N=$r=,=)=%="> 7>!X>z>>>">>!?&?A?V?j???????@.@*F@1q@S@$@>A[A)oAAA.A#A B>B^BwBBBABC'C::C:uC4CBCK(DMtDCD3E,:E#gEHE&EE&F@FZF:sFF'F.F&G=GXGtGfGG H&H9H'NHvHH:H0HI+I-FItI"I I+I4I0J%IJoJ=J#J J1K@KYKqK'KKKKKL/,L\LVlL\L M2:M.mM M2MMM*NF2NyNNHNNO O9OXOCoO'O8O8P8MP8P8P9P82Q7kQ8Q+Q*R*3R+^R"RR8RRR,LSySS*S4S;TNThTTT"TT(T"U4U4IU%~UU/UUU+V7BV/zVVVVVW.WJWeW!|W)WWWW0X!OX'qX4X4X-Y1YBY \Y}YY Y8YYZ,!ZNZ!cZZ!ZZZZ[[ 4[ U[!v[#[[ [[\6\'P\(x\ \1\1\(&]%O]*u]]]]]^3^"N^q^>^)^$^_9_'X_7_6__ `&)`P`o`5```,`'aGaVaga0a)a4a4bJbB^bAb3bCc8[c>c>c-d-@d'ndLd4d5e+NezeVee+eH+fAtffJf+g*@gkgJ~g>g0h%9h(_h(h'hhXhXRi6iJi.-j$\j(jj$j*j!k%7k<]k:k!kkGl^lzll.l!ll,m0mIm^mvmmmm m&m#m!n'&n Nn [nhnqnnnnn8nn oo7oFo`oxoooo&o.o )p(6p_pzpp p"pp2p+qAq Yqcqyqqq%q%q r;+rgrrrrrr r&r s(s7sRs&os4sBs&t15tgttt6t!t uu2uAuXusuu uu u u3uv-vLv$iv vv6vww=w0[ww2w8w(x>xGTx&x/xxy%y7y Gy+hyyyy yGy6z*Vz!zz,z(z2{8J{){{/{ {(|?|*[|.|s|Q)}3{}<}'}~22~,e~!~#~#~(~%4@:u%$+'*?&j/"'5 %BDh!ρ-6Q0k$ʂ#$78%p*098,&e'ӄ#"'Jj($ ؅18+*d=%͆7+I6f30чHDK39Ĉ'&0=&n//ʼn(@R_KOQN4Ջ#݋-/O5n?4#S+w*A΍<?M('-ގ ($@e!0#$6=[8Ґ9 7C/{2ޑ!@@R:6Β68T1,@>1-ɔ0 (I'`5 ˕ڕ! G b""#ɖ3! 36=t ( 2͗2430h/)ɘ93-a0x600/B*r5.Ӛ# &GE^";Ǜ3#!W!y#2//" R*s9؝(5'^2ўG1#Im3;#(9bt: ݠ*)=Wk))֡(')B+lF+ߢ% V1013!!A'cA-ͤ#Kk#'ǥ)  :[ x $צ0-"LFo&˧"#5"Y$|!!è (/.E1t-?ԩ-<B!ت!*6Aa95ݫ(B\qDˬ022L*IA K6[<(Ϯ!:9VQ$Nj.p-԰@AC&24߱K<`"95!0CRF.ݳ0 0=+nL#& '2 Z*f4*Ƶ-6.V'%6Ӷ( /3 cn70,C]'ɸF$^4I-0"K<n4D*% PBq&ۻB4%(Z;0)+F*c))201FxU(" .3@.t/,ӿ+5,b~0B6U,r:;'5 ]/~$3 3(&\75'(*BmC6( 79X: $!4)I)s1-&,$-Q,&)2-0+^\+/1aNy".@7[98-/4:d8{)TA~3od!)J=AY9"-;&4b7F=;Cy0.0;N2:5J.+y(02J-c,<<8M,_&'/0 /<l9&%! *+Vi>% )F$f%,03+_'|$+;%19W<4"&@[Fv%22!Ln"% )$-"R*u7&-L%l%")2+\(86!!,Cp %$ )%Bh$#((G;p"'E"[~(#<`r$0M'a72 =!]L3O$a &&7N`w@/*$F"k&.( ;,N{! & 9Zr:/*G_/u*67Ts )F ^>'T"|%))2E&[0%!#3W&s !1 ?%^'"%+,2+_0"2D!a-2G]t&9Mbx&>Rg| "9Nf<2Ex75BB;"~=<1 N!o  K( 127d%#!'&1N)'5;4D(y'6!;#]#0".6G;~"$0K3<:-=%3c,=!*8 c(8-#''K\sN -@+n  +- E O G j  q7 } , C1   i gm: m Ub a  (ct E 5PU  R I ] %=   P p  / 5I c; j \{ $h'[ F [ r { Z #0 ! # (b  z)| @| 2*L z g Z 7 )t  W  ` R  7<J$ L qD !,+~ 2 n9 - ^  J:  #    7 # w b iVT q   gM G< ]  y C/n q d  Yx }w  B 1  X  , g/  {  \  hFS # Uih 9= # + ePk 5s % U ] [ 2% wB   5 35sD ] fK zh  (   ( uzD n@ a4q P C; :& |*lE W  B S=  kY >e &  " ,  ;:  ; (@BB $U4|& ^ v<Z  _ i  -   1 e ] .w s ZD) P = / h L @a "  & Vw(  H M g r  dc  1 " +[^F   =Jy F   (].]T  ? v 2 B0I-6WO }  ] ~ Wn}    5L CA A*i f  9 { ?E\ 1 Y0 )G o u ! 9%U/ vqAC.! l$ b( ug O [S B 1{PWG7 5  $Z d O@ _ 5. * 6 ! z ; c  N X|9 H&u{ !#   n  u0 V _ H kw Z8 [ 0 d? U LRn8kJ M  L4v W L t[ S P [ TZ  Y` _%*  : s  G< * g  N< wb   h `s i G & Q,Xc$ oH 2  3q^{ u8 l7  {0 ^!ac _  p!z{ T _M <' 'E ~J 0 )+  8 C s WjY <z4 K- G9 (  9d  9P X qK ~j   \b 5Q ^  /Fm    7N ]  cV, h 6W m V Y~  s K f<?;/% u ) f i   C-  '   > |e h K r 3> / U5  'x @ {c  2 ^y L 9 y s D3  tT X pw qf^4 9  ty 0 g    $Q kfq8Q ^%O/ 8 0  u  1 + H'&;  > Z & T m Wj T8 V  O    NH' f[ t I]~\ Q  Cl) x>gY V * Sp2 K y  Zd< x@ 1N l 3 o%S 3$ w\  1*` \ +M 0 h   N8 i s :Z a V o` X Y8l6 2O 6m $ s .3 :}   4cC t4 O A XY  p H26 nJF$'Z( Nq  0 (iA D|]k>)XnC h ^r d3p ,  ; PH =@U -    &: ) P   x# HJ k   _I *[v ; c  x f :   1U ? Eya s FM h'  z Y \ ef   4%  T@76 H T 2 K.-TF A Q x;V9 m   I pv  ;G < B   BD a$ ou  _{!j[ |}  K    Wy MR   = " Rn ` \  g    rY G 0 N 4ax } C =JC s Y S>R\v k 7 RE " e #  U. B  \  XpfQD!X  v  b c -a,o 8} O At =*  { j r|~  _ Kv tm  . vm ^ n -)7 %  ' : H n }7 "D d #l6.=  n `Q 3 r> {n 3 68 & $+ LP e X } ~bw h   : T z, iI4`K  k  k*9 S hs#  a& 0mI~[ GdQu YM  \5 |YVQ Py = &7  .  b q 5  &  saI E2e >Z : "iK 3QMg R:+P Uu k <  cS~Zp _Ev)  ->  x T ]zrMS   K.  )y Q ` h s t,w f  u 2d ' z 8 k;    /K l   + Ad 7 d   U v !XG f ' [  kx u `O" I oFAs( ^ ? mb n, " C!j /  Z  ) ;  @1 L rod  l` i ,O_ cy    " xq $ P 4xR 4Y 3m 3w4 yjI d v  , 4 gA y | O$ ~ c r `- & a M    _ o ; *  NRW| V Y ?C S  [?m ~ p FH +8Vr +1 Q | e /NW ` R= j6@R  rN  #W  ^  E}' T[ 9 ]N  , _*i p  R a L J S pF } * EJ_ / }N% E "y KA <d" .=4 el eq  FHMg : J# D H W .W{ vXJ ] w5l  S  zu  t66   iQ  ?   7 ` r E < I8 ] B * > r * @'l P z %O  $V$?  0D < B~t r m/t ( !  L @e &D I  ozc~p \ K -+ bo#i _M\h  jk 63 V) 1 W n gqP ZA  w  }Af 8wQ ez  S nD    I J B  Tp #   R8 y%MGO }  @ u C !  ?  6b[%  m ?g   G  2 F DBVO  I^ 2  D!e (a 10 t%>df ^ q +LJ =  H   (  gF T\ > G: Rx 9m AEU&" LZ    0>  MzNbU  v . =   ,_ ') 11 4 ) a9-b   \b 7 G M @   'E /F D>; HoVB " o J` jeb % 2 v f S  3 l ?.j? F ? ? e j ~ T !   pKfto G {^2/" 6w U ,3 ~ r"y h  x N au- + } +  I j# 7E- <| kL= X O A x oR `]|  C o { A  |: ( l cX p x 5 i lSk 56l< .  X  t N5 9BJL>j @  ;Q TI CodeComposer Studio syntax compatibility mode [default is %d] [default is %s] specify variant of 960 architecture -b add code to collect statistics about branches taken -link-relax preserve individual alignment directives so linker can do relaxing (b.out format only) -no-relax don't alter compare-and-branch instructions for long displacements specify variant of SPARC architecture -bump warn when assembler switches architectures -sparc ignored --enforce-aligned-data force .long, etc., to be aligned correctly -relax relax jumps and branches (default) -no-relax avoid changing any jumps and branches %s NDS32-specific assembler options: input file : %s options passed : output file : %s target : %s time stamp : %s TIC4X options: -mcpu=CPU -mCPU select architecture variant. CPU can be: 30 - TMS320C30 31 - TMS320C31, TMS320LC31 32 - TMS320C32 33 - TMS320VC33 40 - TMS320C40 44 - TMS320C44 -mrev=REV set cpu hardware revision (integer numbers). Combinations of -mcpu and -mrev will enable/disable the appropriate options (-midle2, -mlowpower and -menhanced) according to the selected type -mbig select big memory model -msmall select small memory model (default) -mregparm select register parameters (default) -mmemparm select memory parameters -midle2 enable IDLE2 support -mlowpower enable LOPOWER and MAXSPEED support -menhanced enable enhanced opcode support constraint violations for constraint violations EXTENSION is combination of: Registers will not need any prefix. Registers will require a `$'-prefix. emulate output (default %s) Record the cpu type -EB assemble code for a big-endian cpu -EL assemble code for a little-endian cpu -USE_R1 assemble code for no warning message when using temp register r1 -V print assembler version number -Qy, -Qn ignored S390 options: -mregnames Allow symbolic names for registers -mwarn-areg-zero Warn about zero base/index registers -mno-regnames Do not allow symbolic names for registers -m31 Set file format to 31 bit format -m64 Set file format to 64 bit format ops were: %s did you mean this? other valid variant(s): --32/--64/--x32 generate 32bit/64bit/x32 code --MD FILE write dependency information in FILE (default none) --alternate initially turn on alternate macro syntax --debug-prefix-map OLD=NEW map OLD to NEW in debug information --defsym SYM=VAL define symbol SYM to given value --disp-size-default-22 branch displacement with unknown size is 22 bits (default) --disp-size-default-32 branch displacement with unknown size is 32 bits --divide do not treat `/' as a comment character --divide ignored --execstack require executable stack for this object --fatal-warnings treat warnings as errors --fix-v4bx Allow BX in ARMv4 code --gdwarf-2 generate DWARF2 debugging information --gdwarf-sections generate per-function section names for DWARF line information --gstabs generate STABS debugging information --gstabs+ generate STABS debug info with GNU extensions --hash-size= set the hash table size close to --help show this message and exit --itbl INSTTBL extend instruction set to include instructions matching the specifications defined in file INSTTBL --listing-cont-lines set the maximum number of continuation lines used for the output data column of the listing --listing-lhs-width set the width in words of the output data column of the listing --listing-lhs-width2 set the width in words of the continuation lines of the output data column; ignored if smaller than the width of the first line --listing-rhs-width set the max width in characters of the lines from the source file --m32bit-doubles [default] --m32bit-doubles [default] --m64bit-doubles --m64bit-doubles Source code uses 64-bit doubles --march= Generate code for . Valid choices for are v0_v10, v10, v32 and common_v10_v32. --mbig-endian-data --mg10 Enable support for G10 variant --mint-register= --mlittle-endian-data [default] --mno-allow-string-insns --mpid --mrelax --msmall-data-limit --muse-conventional-section-names --muse-renesas-section-names [default] --no-underscore User symbols do not have any prefix. --nocompress-debug-sections don't compress DWARF debug sections --noexecstack don't require executable stack for this object --pic Enable generation of position-independent code. --reduce-memory-overheads prefer smaller memory use at the cost of longer assembly times --size-check=[error|warning] ELF .size directive check (default --size-check=error) --statistics print various measured statistics from execution --strip-local-absolute strip local absolute symbols --target-help show target specific options --traditional-format Use same format as native assembler when possible --underscore User symbols are normally prepended with underscore. --version print assembler version number and exit --warn don't suppress warnings -D produce assembler debugging messages -EB assemble code for a big-endian cpu -EB assemble for a big endian system (default) -EL assemble for a little endian system -EB,-big produce big endian code and data -EL generate code for little endian mode (default) -EB generate code for big endian mode -mwarn-expand warn if pseudo operations are expanded -mxp enable i860XP support (disabled by default) -mintel-syntax enable Intel syntax (default to AT&T/SVR4) -EL assemble code for a little-endian cpu -EL, -mel or -little Produce little endian output -EB, -meb or -big Produce big endian output -mpic Generate PIC -mno-fp-as-gp-relax Suppress fp-as-gp relaxation for this file -mb2bb-relax Back-to-back branch optimization -mno-all-relax Suppress all relaxation for this file -EL,-little produce little endian code and data -I DIR add DIR to search list for .include directives -Ip synonym for -ignore-parallel-conflicts -J don't warn about signed overflow -K warn when differences altered for long displacements -KPIC generate PIC -L,--keep-locals keep local symbols (e.g. starting with `L') -M,--mri assemble in MRI compatibility mode -N Warn when branches are expanded to jumps. -O try to optimize code. Implies -parallel -O1, Optimize for performance -Os Optimize for space -Q ignored -Q ignored -V print assembler version number -Q ignored -V print assembler version number -EB/-EL generate big-endian/little-endian code --32/--64 generate 32bit/64bit code -Q ignored -V print assembler version number -k ignored -R fold data section into text section -V print assembler version number -Qy, -Qn ignored -W --no-warn suppress warnings -Wnp synonym for -no-warn-explicit-parallel-conflicts -Wnuh synonym for -no-warn-unmatched-high -Wp synonym for -warn-explicit-parallel-conflicts -Wuh synonym for -warn-unmatched-high -X ignored -Z generate object file even after errors -c print a warning if a comment is found -f skip whitespace and comment preprocessing -fixed-special-register-names Allow only the original special register names. -g --gen-debug generate debugging information -globalize-symbols Make all symbols global. -gnu-syntax Turn off mmixal syntax compatibility. -h, -H Don't execute, print this help text. Deprecated. -ignore-parallel-conflicts do not check parallel instructions -linker-allocated-gregs If there's no suitable GREG definition for the operands of an instruction, let the linker resolve. -m%s%s -m32r disable support for the m32rx instruction set -m32r2 support the extended m32r2 instruction set -m32rx support the extended m32rx instruction set -m4byte-align Mark the binary as using 32-bit alignment (default) -m8byte-align Mark the binary as using 64-bit alignment -mEA -mbarrel-shifter -mbarrel_shifter -mcrc -mdsp-packa -mdsp_packa -mdvbf -mld-extension-reg-mask -mlock -mmac-24 -mmac-d16 -mmac_24 -mmac_d16 -mmin-max -mmin_max -mmul64 -mno-mpy -mnorm -mrtsc -msimd -mswap -mswape -mtelephony -muser-mode-only -mxy -mN - do not insert NOPs after changing interrupts (default) -mQ - enable relaxation at assembly time. DANGEROUS! -mP - enable polymorph instructions -mY - do not warn about missing NOPs after changing interrupts -m[no-]%-17sEnable/Disable %s -mach= Set the H8300 machine type to one of: h8300h, h8300hn, h8300s, h8300sn, h8300sx, h8300sxn -madd-bnd-prefix add BND prefix for all valid branches -mall-ext Turn on all extensions and instructions support -march=ARCH enable instructions from architecture ARCH -march=CPU[,+EXTENSION...] generate code for CPU and EXTENSION, CPU is one of: -march=ms1-16-002 allow ms1-16-002 instructions (default) -march=ms1-16-003 allow ms1-16-003 instructions -march=ms1-64-001 allow ms1-64-001 instructions -march=ms2 allow ms2 instructions -mavxscalar=[128|256] encode scalar AVX instructions with specific vector length -mbig-endian generate big-endian code -mbig-obj generate big object files -mcpu= specify the name of the target CPU -md - Force copying of data from ROM to RAM at startup -mdsbt code uses DSBT addressing -mevexlig=[128|256|512] encode scalar EVEX instructions with specific vector length -mevexrcig=[rne|rd|ru|rz] encode EVEX instructions with specific EVEX.RC value for SAE-only ignored instructions -mevexwig=[0|1] encode EVEX instructions with specific EVEX.W value for EVEX.W bit ignored instructions -mextension enable extension opcode support -mfdpic assemble for the FDPIC ABI -mgcc-abi Mark the binary as using the old GCC ABI -mindex-reg support pseudo index registers -mintel64 accept only Intel64 ISA -mip2022 restrict to IP2022 insns -mip2022ext permit extended IP2022 insn -ml - enable large code model -mlittle-endian generate little-endian code -mmnemonic=[att|intel] use AT&T/Intel mnemonic -mn - insert a NOP after changing interrupts -mnaked-reg don't require `%%' prefix for registers -mno-bcond17 disable b disp17 instruction -mno-dsbt code does not use DSBT addressing -mno-fdpic/-mnopic disable -mfdpic -mno-pic code addressing is position-dependent -mno-stld23 disable st/ld offset23 instruction -mold-gcc support old (<= 2.8.1) versions of gcc -momit-lock-prefix=[no|yes] strip all lock prefixes -moperand-check=[none|error|warning] check operand combinations for validity -mpic code addressing is position-independent -mpid=far code uses position-independent data addressing, GOT accesses use far DP addressing -mpid=near code uses position-independent data addressing, GOT accesses use near DP addressing -mpid=no code uses position-dependent data addressing -mrelax Enable relaxation -mrh850-abi Mark the binary as using the RH850 ABI (default) -msilicon-errata=[,...] - enable fixups for silicon errata -msilicon-errata-warn=[,...] - warn when a fixup might be needed supported errata names: cpu4, cpu8, cpu11, cpu12, cpu13, cpu19 -msse-check=[none|error|warning] check SSE instructions -msse2avx encode SSE instructions with VEX prefix -msyntax=[att|intel] use AT&T/Intel syntax -mtune=CPU optimize for CPU, CPU is one of: -mv850 The code is targeted at the v850 -mv850e The code is targeted at the v850e -mv850e1 The code is targeted at the v850e1 -mv850e2 The code is targeted at the v850e2 -mv850e2v3 The code is targeted at the v850e2v3 -mv850e2v4 Alias for -mv850e3v5 -mv850e3v5 The code is targeted at the v850e3v5 -mwarn-signed-overflow Warn if signed immediate values overflow -mwarn-unsigned-overflow Warn if unsigned immediate values overflow -my - warn about missing NOPs after changing interrupts (default) -n Do not optimize code alignment -q quieten some warnings -nIp synonym for -no-ignore-parallel-conflicts -no-bitinst disallow the M32R2's extended bit-field instructions -no-expand Do not expand GETA, branches, PUSHJ or JUMP into multiple instructions. -no-ignore-parallel-conflicts check parallel instructions for -no-merge-gregs Do not merge GREG definitions with nearby values. -no-parallel disable -parallel -no-predefined-syms Do not provide mmixal built-in constants. Implies -fixed-special-register-names. -no-warn-explicit-parallel-conflicts do not warn when parallel -no-warn-unmatched-high do not warn about missing low relocs -nocpp ignored -nosched disable scheduling restrictions -o OBJFILE name the object-file output OBJFILE (default a.out) -parallel try to combine instructions in parallel -relax Create linker relaxable code. -s ignored -w ignored -warn-explicit-parallel-conflicts warn when parallel instructions -warn-unmatched-high warn when an (s)high reloc has no matching low reloc -x Do not warn when an operand to GETA, a branch, PUSHJ or JUMP is not known to be within range. The linker will catch any errors. Implies -linker-allocated-gregs. -xauto automagically remove dependency violations (default) -xnone turn off dependency violation checking -xdebug debug dependency violation checker -xdebugn debug dependency violation checker but turn off dependency violation checking -xdebugx debug dependency violation checker and turn on dependency violation checking @FILE read options from FILE %s; *input_line_pointer == '%c' 0x%02x AArch64-specific assembler options: ARM-specific assembler options: Blackfin specific assembler options: FR30 specific command line options: GNU assembler version %s (%s) using BFD version %s. M32C specific command line options: M32R specific command line options: MMIX-specific command line options: Meta specific command line options: RL78 specific command line options: RX specific command line options: Score-specific assembler options: V850 options: XC16X specific command line options: XSTORMY16 specific command line options: Z8K options: -z8001 generate segmented code -z8002 generate unsegmented code -linkrelax create linker relaxable code !%s does not use a sequence number!samegp reloc against symbol without .prologue: %s"%d" (instance number %d of a %s label)".else" without matching ".if"".elseif" after ".else"".elseif" without matching ".if"".endif" without ".if"# Example of `%s' instructions .sect .text _start: # bars register# conflicts length#4 not valid on H8/300.###$DPR_BYTE not supported in this context$DPR_GOT not supported in this context$DPR_HWORD not supported in this context$DPR_WORD not supported in this context$DSBT_INDEX must be used with __c6xabi_DSBT_BASE$DSBT_INDEX not supported in this context$GOT not supported in this context$PCR_OFFSET not supported in this context$dbg and $depc are disabled when DEBUG is off$hi and $lo are disabled when MUL and DIV are off$mb0, $me0, $mb1, and $me1 are disabled when COP is off% operator needs absolute expression%%%s() must be outermost term in expression%%hi16/%%lo16 only applies to .short or .hword%%hi8 only applies to .byte%d error%d errors%d warning%d warnings%s %s -- `%s'%s -- statement `%s' ignored%s NOP inserted%s `%s' already has an alias `%s'%s argument must be a string%s at operand %d -- `%s'%s for `%s'%s instruction does not accept a .b suffix%s instruction, operand %d doesn't match%s is enabled by vle flag%s is not used for the selected target%s may not occupy the delay slot of another branch insn.%s must have a constant value%s not disabled by vle flag%s not supported in MIPS16 mode%s offset %d out of range %d to %d%s out of domain (%d is not a multiple of %d)%s out of range %d to %d at operand %d -- `%s'%s out of range (%d is not between %d and %d)%s out of range (0x%s is not between 0x%s and 0x%s)%s register same as write-back base%s relocations do not fit in %d bytes%s relocations do not fit in %d bytes %s relocations do not fit in %u bytes %s second argument cannot be a negative number %d%s shortened to %s%s symbol recursion stopped at second appearance of '%s'%s unsupported%s without %s%s, %s, generating bad object file %s, treating warnings as errors%s: attempt to rotate the PC register%s: data size %ld %s: global symbols not supported in common sections%s: no such section%s: output of 1st instruction is the same as an input to 2nd instruction - is this intentional ?%s: output of 2nd instruction is the same as an input to 1st instruction - is this intentional ?%s: total time in assembly: %ld.%06ld %s: unexpected function type: %d%s: unrecognized processor name%s: would close weakref loop: %s%s:%u: bad return from bfd_install_relocation: %x%u-byte relocation cannot be applied to %u-byte field'%.*s' instruction not at start of execute packet'%.*s' instruction not in a software pipelined loop'%.*s' instruction not supported on this architecture'%.*s' instruction not supported on this functional unit'%.*s' instruction not supported on this functional unit for this architecture'%s' can't be a weak_definition (currently only supported in sections of type coalesced)'%s' can't be a weak_definition (since it is undefined)'%s' is not repeatable. Resulting behavior is undefined.'%s' is only available in DD2.0 or higher.'%s' may not be bundled with other instructions.'%s' previously declared as '%s'.'%s': only the NOP instruction can be issued in parallel on the m32r')' required',' expected'APSR', 'CPSR' or 'SPSR' expected'ASR' required'H' modifier only valid for accumulator registers'L' modifier not valid for this instruction'LSL' or 'ASR' required'LSL' required'MFC_RdTagMask' (channel 12) is only available in DD2.0 or higher.'P', 'N' or 'Z' flags may only be specified when accumulating'ROR' shift is not permitted'SPU_RdEventMask' (channel 11) is only available in DD2.0 or higher.'[' expected'[' expected after PLD mnemonic'[' expected after PLI mnemonic']' expected'd.%s' must be 8-byte aligned'entry_num' must be absolute number in [0,31]'||' after predicate'||' not followed by instruction'||^' without previous SPMASK'}' expected at end of 'option' field(PC)+ unpredictable(plt) is only valid on branch targets(unknown reason)*-%s conflicts with the other architecture options, which imply -%s-(PC) unpredictable-- unterminated string--abi=[32|64] set size of expanded SHmedia operands and object file type --shcompact-const-crange emit code-range descriptors for constants in SHcompact code sections --no-mix disallow SHmedia code in the same section as constants and SHcompact code --no-expand do not expand MOVI, PT, PTA or PTB instructions --expand-pt32 with -abi=64, expand PT, PTA and PTB instructions to 32 bits only --absolute-literals option not supported in this Xtensa configuration--density option is ignored--fdpic generate an FDPIC object file --generics is deprecated; use --transform instead--gstabs is not supported for ia64--hash-size needs a numeric argument--isa=[shmedia set as the default instruction set for SH64 | SHmedia | shcompact | SHcompact] --no-density option is ignored--no-generics is deprecated; use --no-transform instead--no-relax is deprecated; use --no-transform instead--no-underscore is invalid with a.out format--nops needs a numeric argument--pic is invalid for this object format--relax is deprecated; use --transform instead-32 create 32 bit object file -64 create 64 bit object file -32 create o32 ABI object file (default) -n32 create n32 ABI object file -64 create 64 ABI object file -EL generate code for a little endian machine -EB generate code for a big endian machine --little-endian-data generate code for a machine having big endian instructions and little endian data. -G may not be used in position-independent code-G may not be used with SVR4 PIC code-G n Put data <= n bytes in the small data area -G not supported in this configuration-KPIC, -call_shared generate SVR4 position independent code -call_nonpic generate non-PIC code that can operate with DSOs -mvxworks-pic generate VxWorks position independent code -non_shared do not generate code that can operate with DSOs -xgot assume a 32 bit GOT -mpdr, -mno-pdr enable/disable creation of .pdr sections -mshared, -mno-shared disable/enable .cpload optimization for position dependent (non shared) code -mabi=ABI create ABI conformant object file for: -R option not supported on this target.-TSO use Total Store Ordering -PSO use Partial Store Ordering -RMO use Relaxed Memory Ordering -expand-pt32 invalid together with -no-expand-expand-pt32 only valid with -abi=64-k generate PIC -l use 1 word for refs to undefined symbols [default 2] -pic, -k generate position independent code -S turn jbsr into jsr --pcrel never turn PC-relative branches into absolute jumps --register-prefix-optional recognize register names without prefix character --bitwise-or do not treat `|' as a comment character --base-size-default-16 base reg without size is 16 bits --base-size-default-32 base reg without size is 32 bits (default) --disp-size-default-16 displacement with unknown size is 16 bits --disp-size-default-32 displacement with unknown size is 32 bits (default) -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated. -no-mCPU don't generate code specific to CPU. For -mCPU and -no-mCPU, CPU must be one of: -mPIC Mark generated file as using large position independent code -maltivec generate code for AltiVec -mvsx generate code for Vector-Scalar (VSX) instructions -mhtm generate code for Hardware Transactional Memory -me300 generate code for PowerPC e300 family -me500, -me500x2 generate code for Motorola e500 core complex -me500mc, generate code for Freescale e500mc core complex -me500mc64, generate code for Freescale e500mc64 core complex -me5500, generate code for Freescale e5500 core complex -me6500, generate code for Freescale e6500 core complex -mspe generate code for Motorola SPE instructions -mvle generate code for Freescale VLE instructions -mtitan generate code for AppliedMicro Titan core complex -mregnames Allow symbolic names for registers -mno-regnames Do not allow symbolic names for registers -march=%s is not compatible with the selected ABI-march= set architecture -mcpu= set cpu [default %s] -mcpu= Specify the CPU version -mcpu={fr500|fr550|fr400|fr405|fr450|fr300|frv|simple|tomcat} -mdouble Mark generated file as using double precision FP insns -mdsp generate DSP instructions -mno-dsp do not generate DSP instructions -mdspr2 generate DSP R2 instructions -mno-dspr2 do not generate DSP R2 instructions -mdword Mark generated file as using a 8-byte stack alignment -me Redirect errors to a file -merrors-to-file -mfar-mode | -mf Use extended addressing -mfdpic Assemble for the FDPIC ABI -mfix-loongson2f-jump work around Loongson2F JUMP instructions -mfix-loongson2f-nop work around Loongson2F NOP errata -mfix-vr4120 work around certain VR4120 errata -mfix-vr4130 work around VR4130 mflo/mfhi errata -mfix-24k insert a nop after ERET and DERET instructions -mfix-cn63xxp1 work around CN63XXP1 PREF errata -mgp32 use 32-bit GPRs, regardless of the chosen ISA -mfp32 use 32-bit FPRs, regardless of the chosen ISA -msym32 assume all symbols have 32-bit values -O0 remove unneeded NOPs, do not swap branches -O remove unneeded NOPs and swap branches --trap, --no-break trap exception on div by 0 and mult overflow --break, --no-trap break exception on div by 0 and mult overflow -mfpr-32 Mark generated file as only using 32 FPRs -mfpr-64 Mark generated file as using all 64 FPRs -mgpr-32 Mark generated file as only using 32 GPRs -mgpr-64 Mark generated file as using all 64 GPRs -minsn32 only generate 32-bit microMIPS instructions -mno-insn32 generate all microMIPS instructions -mips1 generate MIPS ISA I instructions -mips2 generate MIPS ISA II instructions -mips3 generate MIPS ISA III instructions -mips4 generate MIPS ISA IV instructions -mips5 generate MIPS ISA V instructions -mips32 generate MIPS32 ISA instructions -mips32r2 generate MIPS32 release 2 ISA instructions -mips32r3 generate MIPS32 release 3 ISA instructions -mips32r5 generate MIPS32 release 5 ISA instructions -mips32r6 generate MIPS32 release 6 ISA instructions -mips64 generate MIPS64 ISA instructions -mips64r2 generate MIPS64 release 2 ISA instructions -mips64r3 generate MIPS64 release 3 ISA instructions -mips64r5 generate MIPS64 release 5 ISA instructions -mips64r6 generate MIPS64 release 6 ISA instructions -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of: -mips16 generate mips16 instructions -no-mips16 do not generate mips16 instructions -mips16 cannot be used with -micromips-mmcu generate MCU instructions -mno-mcu do not generate MCU instructions -mmedia Mark generated file as using media insns -mmicromips generate microMIPS instructions -mno-micromips do not generate microMIPS instructions -mmicromips cannot be used with -mips16-mmsa generate MSA instructions -mno-msa do not generate MSA instructions -mmt generate MT instructions -mno-mt do not generate MT instructions -mmuladd Mark generated file as using multiply add/subtract insns -mno-dword Mark generated file as using a 4-byte stack alignment -mno-pack Do not allow instructions to be packed -mnopic Disable -mpic, -mPIC, -mlibrary-pic and -mfdpic -mpack Allow instructions to be packed -mpic Mark generated file as using small position independent code -mrelocatable support for GCC's -mrelocatble option -mrelocatable-lib support for GCC's -mrelocatble-lib option -memb set PPC_EMB bit in ELF flags -mlittle, -mlittle-endian, -le generate code for a little endian machine -mbig, -mbig-endian, -be generate code for a big endian machine -msolaris generate code for Solaris -mno-solaris do not generate code for Solaris -K PIC set EF_PPC_RELOCATABLE_LIB in ELF flags -V print assembler version number -Qy, -Qn ignored -msmartmips generate smartmips instructions -mno-smartmips do not generate smartmips instructions -msoft-float Mark generated file as using software FP -mtomcat-debug Debug tomcat workarounds -mtomcat-stats Print out stats for tomcat workarounds -mvirt generate Virtualization instructions -mno-virt do not generate Virtualization instructions -mxpa generate eXtended Physical Address (XPA) instructions -mno-xpa do not generate eXtended Physical Address (XPA) instructions -no-expand only valid with SHcompact or SHmedia-no-mix is invalid without specifying SHcompact or SHmedia-nops=count when aligning, more than COUNT nops uses a branch -ppc476-workaround warn if emitting data to code sections -shcompact-const-crange is invalid without SHcompact.%s outside of %s....COMMon length (%d.) < 0! Ignored..COMMon length (%ld.) <0! Ignored..COMMon length (%lu) out of range ignored.EQU must use a label.EXIT must appear within a procedure.REG expression must be a register.REG must use a label.SCOMMon length (%ld.) <0! Ignored..abiversion expression does not evaluate to a constant.abort detected. Abandoning ship..arch requires a matching --march=... option.asmfunc pseudo-op only available with -mccs flag..asmfunc repeated..asmfunc without function..begin [no-]density is ignored.begin directive with no matching .end directive.begin directive without a preceding .ent directive.begin directive without a preceding .file directive.begin literal is deprecated; use .literal instead.begin/.bend in different segments.bend directive names unknown symbol.bend directive without a preceding .ent directive.bend directive without a preceding .file directive.bss size %d < 0!.bss size %ld < 0!.bss size argument missing .bundle_align_mode alignment too large (maximum %u).bundle_lock is meaningless without .bundle_align_mode.bundle_lock sequence at %u bytes but .bundle_align_mode limit is %u bytes.bundle_lock sequence is %u bytes, but bundle size only %u.bundle_lock with no matching .bundle_unlock.bundle_unlock without preceding .bundle_lock.callinfo is not within a procedure definition.cfi_endproc without corresponding .cfi_startproc.cfi_inline_lsda seen for frame without .cfi_lsda.cfi_lsda requires encoding and symbol arguments.cfi_personality requires encoding and symbol arguments.compiler directive missing language and version.compiler directive missing version.cpload not in noreorder section.def pseudo-op only available with -mccs flag..def pseudo-op used inside of .def/.endef: ignored..def pseudo-op used inside of .def/.endef; ignored.dim pseudo-op used outside of .def/.endef: ignored..dim pseudo-op used outside of .def/.endef; ignored.ef with no preceding .function.end [no-]density is ignored.end directive has no name.end directive missing or unknown symbol.end directive names different symbol than .ent.end directive names unknown symbol.end directive without a preceding .ent directive.end directive without a preceding .ent directive..end directive without a preceding .file directive.end directive without matching .ent.end not in text section.end symbol does not match .ent symbol.end symbol does not match .ent symbol..end%c encountered without preceding %s.end%s without preceding .%s.endasmfunc pseudo-op only available with -mccs flag..endasmfunc without a .asmfunc..endasmfunc without function..endef pseudo-op used before .def; ignored.endef pseudo-op used outside of .def/.endef: ignored..endfunc missing for previous .func.endfunc missing for previous .proc.ent directive has no name.ent directive has no symbol.ent directive without matching .end.ent or .aent not in text section.ent or .aent not in text section..err encountered.error directive invoked in source file.es without preceding .bs.fail %ld encountered.field count '%d' out of range (1 <= X <= 32).fill size clamped to %d.fmask outside of .ent.fnend directive without .fnstart.frame outside of .ent.gnu_attribute %d,%d is incompatible with `%s'.gnu_attribute %d,%d is no longer supported.gnu_attribute %d,%d is not a recognized floating-point ABI.gnu_attribute %d,%d requires `%s'.handler directive has no name.ifeqs syntax error.incbin count zero, ignoring `%s'.inst.n operand too big. Use .inst.w instead.largecomm supported only in 64bit mode, producing .comm.linkonce is not supported for this object file format.literal not allowed inside .begin literal region.literal_position inside literal directive; ignoring.ln pseudo-op inside .def/.endef: ignored..loc before .file.loc outside of .text.loc pseudo-op inside .def/.endef: ignored..localentry expression for `%s' does not evaluate to a constant.localentry expression for `%s' is not a valid power of 2.longcall pseudo-op seen when not relaxing.longjump pseudo-op seen when not relaxing.ltorg in section %s paired to .using in section %s.ltorg without prior .using in section %s.machine stack overflow.machine stack underflow.machinemode stack overflow.machinemode stack underflow.mask outside of .ent.mask/.fmask outside of .ent.module is not permitted after generating code.module used with unrecognized symbol: %s .name directive has no symbol.name directive not in link (.link) section.option pic%d not supported.pdesc directive has no entry symbol.pdesc directive not in link (.link) section.pdesc doesn't match with last .ent.pdesc has a bad entry symbol.popsection without corresponding .pushsection; ignored.previous without corresponding .section; ignored.profiler pseudo requires at least two operands..prologue directive without a preceding .ent directive.prologue within prologue.ref outside .csect.ref pseudo-op only available with -mccs flag..sblock may be used for initialized sections only.scl pseudo-op used outside of .def/.endef; ignored.sect: subsection name ignored.set pop with no .set push.set syntax invalid .size expression for %s does not evaluate to a constant.size pseudo-op used outside of .def/.endef; ignored.space or .fill with negative value, ignored.space repeat count is negative, ignored.space repeat count is zero, ignored.space specifies non-absolute value.space/.bes repeat count is negative, ignored.space/.bes repeat count is zero, ignored.stab%c is not supported.stab%c: description field '%x' too big, try a different debug format.stab%c: ignoring non-zero other field.stab%c: missing comma.stabx of storage class stsym must be within .bs/.es.syntax %s requires command-line option `--no-underscore'.syntax %s requires command-line option `--underscore'.tag pseudo-op used outside of .def/.endef; ignored.tag requires a structure tag.tag target '%s' undefined.tc not in .toc section.tc with no label.type pseudo-op used outside of .def/.endef; ignored.unwind_save does not support this kind of register.usect: non-zero alignment flag ignored.usepv directive has no name.usepv directive has no type.uses does not refer to a local symbol in the same section.uses pseudo-op seen when not relaxing.uses target does not refer to a local symbol in the same section.using: base address expression illegal or too complex.val expression is too complex.val pseudo-op used outside of .def/.endef; ignored.var may only be used within a macro definition.vframepsp is meaningless, assuming .vframesp was meant.vliw unavailable when VLIW is disabled..warning directive invoked in source file.word %s-%s+%s didn't fit.word case-table handling failed: table too large0x%lx out range of signed 32bit displacement0x%lx: "%s" type = %ld, class = %d, segment = %d 128-bit SIMD scalar or floating-point quad precision register expected16-bit SIMD scalar or floating-point half precision register expected16-bit extension16-bit jump out of range16-bit relocation used in 8-bit operand3-bit immediate out of range32-bit SIMD scalar or floating-point single precision register expected32-bit address isn't allowed in 64-bit MPX instructions.32-bit conditional branch generated32bit mode not supported on `%s'.32bit x86_64 is only supported for ELF5-bit field must be absolute5-bit immediate too large6-bit displacement out of range6-bit immediate out of range62-bit relocation not yet implemented64-bit SIMD scalar or floating-point double precision register expected64bit mode not supported on `%s'.68040 and 68851 specified; mmu instructions may assemble incorrectly8-bit SIMD scalar register expected8-bit displacement out of range8-bit immediate out of range8-bit relocation used in 16-bit operand: Immediate value in cbcond is out of range.: Instruction requires frs2 and frsd must be the same register: PC-relative operand can't be a constant: TLS operand can't be a constant: There are only 32 f registers; [0-31]: There are only 32 single precision f registers; [0-31]: There are only 64 f registers; [0-63]: asr number must be between 0 and 31: crypto immediate must be between 0 and 31: expected register name ccr : expected register name pc : expected register name r0-r7 : expecting %asrN: expecting crypto immediate: invalid ASI expression: invalid ASI name: invalid ASI number: invalid cpreg name: invalid membar mask expression: invalid membar mask name: invalid membar mask number: invalid prefetch function expression: invalid prefetch function name: invalid prefetch function number: invalid siam mode expression: invalid siam mode number: processing macro, real opcode handle not found in hash: unrecognizable hyperprivileged register: unrecognizable privileged register:b not permitted; defaulting to :w:operand has too many bits:operand value(%d) too big for constraint:unknown relocation constraint size specify for ABI Specify a abi version could be v1, v2, v2fp, v2fpp assemble for floating point ABI Assemble for architecture could be v3, v3j, v3m, v3f, v3s, v2, v2j, v2f, v2s assemble for architecture Assemble for baseline could be v2, v3, v3m assemble for CPU assemble for DSP architecture assemble for FPU architecture Specify a FPU configuration 0: 8 SP / 4 DP registers 1: 16 SP / 8 DP registers 2: 32 SP / 16 DP registers 3: 32 SP / 32 DP registers,X